Wednesday, August 08, 2012 | Raymond G. Clark and Joseph D. Poole, TT electronics – IMS
Editor's Note: This article originally appeared in the July 2012 issue of SMT Magazine.
Miniaturization continues to be a driving force in both integrated circuit packaging and PCB laminate technology. In addition to decreasing component pitch (lead-to-lead spacing), utilization of the vertical space by stacking packages has found wide acceptance by both designers and manufactures of electronics alike. Lead-free package-on-package (PoP) technology represents one of the latest advancements in vertical electronics packaging integration and has become the preferred technology for mobile handheld electronics applications. TT electronics in Perry, Ohio, has developed the capability to assemble and rework numerous state-of-the-art packaging technologies. This article will focus on the essential engineering development activities performed to demonstrate TT electronics’ ability to both assemble and rework PoP components.
For many years peripherally-leaded packages were at the forefront of electronic packaging technology. In those days the main purpose of integrated circuit (IC) packaging was to protect the device inside from environmentally induced corrosion, provide mechanical protection, and provide an electrical path to the printed circuit board. This strategy proved effective until ever-increasing lead counts made the peripherally-leaded package impractical. The introduction of area array packaging technology solved this problem. In today’s area array packaging, the leads are distributed across the entire surface of the package in a rectangular array fashion (Figure 1). Thus, a larger I/O count can be accommodated in a smaller area package. In fact, the area required for a peripherally leaded package increases exponentially with lead count while the area array package shows a linear dependence (Figure 2).
In recent years the stacked packaging structure has found acceptance in the mobile handheld electronic market. By combining logic and memory chips into the same stacked package, designers can fit more function into a smaller and lighter form. The two predominant forms of stacked packaging structures are: the stacked die stricture and the PoP structure (Figure 3)1.
Figure 1: Illustrates the difference between QFP and BGA packages, showing an ultra-fine-pitch 160 lead QFP (pitch 0.3 mm) on a background consisting of the bottom side of a 1.5 mm pitch PBGA with 225 interconnection solder balls. From this picture it is easy to understand the popularity this BGA package has received among the people in the assembly business. Note that there are five QFP leads for every BGA solder sphere.