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In the last edition of The Pulse, we began a discussion on how a modern field solver can help choose the most cost-effective material for a high-frequency application. Recall that we asked what characteristics of materials, from an ultra-high-speed digital perspective, most affect signal integrity.
Continuing the theme of Part 1, in this month’s column we use the graphical presentation of losses versus frequency of a lossy line field solver to decide on the best choices for material selection. Last month we looked briefly at the effects of line length and dielectric losses, and this month we focus on copper losses; all three are primary drivers for losses.
Our decision on the best material for the application will, as ever, be a trade-off between cost and signal integrity performance. The frequency-dependent graphing of a lossy line field solver is especially useful because PCB materials are increasingly required to support high-speed serial communications at speeds where signal loss becomes the prime characteristic compromising signal integrity.
Manufacturers claim chipset transmission performance that will enable a specified "loss budget” which must not be exceeded if the circuit is to operate at maximum data rates. Our graphs show losses versus frequency drawn against a line showing the acceptable loss budget.
Two methods should be used when looking at copper losses (conductor loss) due to cross-sectional area. First, you can extract the conductor losses and ignore the effects of roughness. Microwave designers used to minimise these losses by achieving their required impedance with wide traces and large dielectric separations. However, in digital designs device physical dimensions usually limit your freedom on line widths.
The following graphics illustrate the surface roughness profiles and surfaces for regular and ultra-flat foils.
Figure 1: Regular profile foil cross section RZ = 6 – 10 microns (Image courtesy of Circuit Foil Luxembourg)
Figure 2: Regular profile foil surface RZ = 6 – 10 microns (Image courtesy of Circuit Foil Luxembourg)
Figure 3: Ultra-flat profile foil cross section RZ = 3 microns (Image courtesy of Circuit Foil Luxembourg)
Figure 4: Ultra-flat profile foil surface RZ = 3 microns (Image courtesy of Circuit Foil Luxembourg).Modelling Surface Roughness
Second, you can add in the modelling which calculates the losses due to the RMS roughness (in this case a physical dimension--not a voltage!), i.e., the RMS of the peak-to-trough height variation on the copper surface. It could be that by using a smoother copper you can save money with a lower-performing dielectric material. However, you need to model each case to find which of the above is the main influencer in your design.
The graphs below show how a typical range of values for RMS roughness (0.6 µm (0.02 mils) for stripline, 1.6µm (0.06 mils) for surface microstrip) can prove the difference between meeting or exceeding the loss budget for 40 inch total trace length. Some counterintuition here can help from time to time, as one side of the copper (drum side) is typically smoother than the other, and often the rougher side will be bonded to the core material. To minimise loss from surface roughness it may help to place the critical structures in the stackup so the smooth faces are the closest in a structure.
Figure 5: 0.6 µm (0.02 mils) RMS roughness.
Figure 6: 1.6 µm (0.06 mils) RMS roughness.The Commercial Approach
From the design authority's perspective it may seem best to "lock down" to a very tight material spec, possibly even specifying the brand and type of material to be used. This approach does have its place, but it is also valuable to consider allowing the fabricator more freedom to choose materials and take a more generic approach by specifying the material choice according to IPC slash sheets.
From the fabricator's perspective a tightly specified material requirement makes the specification very easy to interpret but leaves no freedom to work on the best cost/material trade off. Another benefit of a more generic specification of materials is the ability to substitute an equivalent in times of material shortage or lengthening lead times.
The choices outlined above can come down to company policy or the regulatory environment of the end-use product; however, it is always worth keeping an open discussion channel between the three parties: laminate supplier, PCB field applications engineer and the original design specifier.
What if you don't use modelling tools to explore your design space? Chances are that you will pay more than necessary to bring your product to market, or, even worse, discover that the design struggles to meet its high-speed performance specifications.
Using a lossy line field solver will help your discussions between fabricator and supplier result in the most cost-effective material choice and stackup design for your chosen application and allow, where possible, rapid material substitution in the event of material price rises or shortage of supply.
Hopefully, these two parts of The Pulse will help you find the best cost/performance stackup and material selection and make the process easier than finding The Chemical Brothers on my iPod.
Figures 1-4 are used by kind permission of Circuit Foil Luxembourg.